A PTAS for the minimum dominating set problem in unit disk graphs

We present a polynomial-time approximation scheme (PTAS) for the minimum dominating set problem in unit disk graphs. In contrast to previously known approximation schemes for the minimum dominating set problem on unit disk graphs, our approach does not assume a geometric representation of the vertices (specifying the positions of the disks in the plane) to be given as part of the input. \u

On cyclic plans for scheduling a smart card personalisation system

An industrial case study for scheduling the personalisation of smart cards is presented and analysed. Smart cards are personalised in several machines that are served by an underlying conveyor belt connecting these. As there are usually a very high number of smart cards to be personalised, the focus is on cyclic schedules and the goal is to obtain a plan with high throughput. By characterizing certain schedules by the number of cards and free slots on the conveyor belt per cycle, non-trivial bounds on the cycle-time, and thus on the throughput, can be provided. This is done by looking at certain special scheduling policies, and using techniques known as destructive bounding. Additionally, with respect to the case study, optimality is proven for the input instances provided

Job-shop scheduling with limited capacity buffers

In this paper we investigate job-shop problems where limited capacity buffers to store jobs in non-processing periods are present. In such a problem setting, after finishing processing on a machine, a job either directly has to be processed on the following machine or it has to be stored in a prespecified buffer. If the buffer is completely occupied the job may wait on its current machine but blocks this machine for other jobs. Besides a general buffer model, also specific configurations are considered. The aim of this paper is to find a compact representation of solutions for the job-shop problem with buffers. In contrast to the classical job-shop problem, where a solution may be given by the sequences of the jobs on the machines, now also the buffers have to be incorporated in the solution representation. In a first part, two such representations are proposed, one which is achieved by adapting the alternative graph model and a second which is based on the disjunctive graph model. In a second part, it is investigated whether the given solution representation can be simplified for specific buffer configurations. For the general buffer configuration it is shown that an incorporation of the buffers in the solution representation is necessary, whereas for specific buffer configurations possible simplifications are presented

Collaborative communication protocols for wireless sensor networks

In this document, the design of communication within a wireless sensor network is discussed. The resource limitations of such a network, especially in terms of energy, require an integrated approach for all (traditional) layers of communication. We present such an integrated, collaborative approach which is part of current research in the European research project EYES on energy-efficient sensor networks. In particular, energy-efficient solutions for medium access control, clusterbased routing and multipath routing are discussed. As part of the ongoing project, these approaches work together and are designed to support each other

Via Minimization in VLSI Chip Design - Application of a Planar Max-Cut Algorithm

The design of very large scale integrated (VLSI) chips is an exciting area of applied discrete mathematics.Due to the intractability of the majority of the problems, and also due to the huge instance sizes, the design process is decomposed into various sub-problems. In this paper, for a given detailed routing solution, we revisit the assignment of layers to net segments. For connected metalized nets, a layer change is accomplished by a vertical interconnection area (via). We seek to minimize the use of these vias as vias not only reduce the electrical reliability and performance of the chip, but also decrease the manufacturing yield substantially. In the general case, the via minimization problem is NP-hard. However, it is known that the two layer via minimization problem can be solved as a maximum cut problem on a planar graph which is a polynomial task.The focus of this paper is to use this approach for modern real-world chips. From the roughly two dozen wiring layers present, we take two adjacent ones for the via minimization. As a core-routine, we use a fast maximum cut algorithm on planar graphs. For being able to use the solutions in practice, we integrate practically relevant design rule constraints at the expense of potentially using further vias. Thus, our solution satisfies the additional constraints present in actual current designs. The computational results show that our implementation is fast on real-world instances as it usually computes a solution within a few minutes CPU time only. Moreover, often a considerable amount of vias can be saved

Via Minimization in VLSI Chip Design - Application of a Planar Max-Cut Algorithm

The design of very large scale integrated (VLSI) chips is an exciting area of applied discrete mathematics.Due to the intractability of the majority of the problems, and also due to the huge instance sizes, the design process is decomposed into various sub-problems. In this paper, for a given detailed routing solution, we revisit the assignment of layers to net segments. For connected metalized nets, a layer change is accomplished by a vertical interconnection area (via). We seek to minimize the use of these vias as vias not only reduce the electrical reliability and performance of the chip, but also decrease the manufacturing yield substantially. In the general case, the via minimization problem is NP-hard. However, it is known that the two layer via minimization problem can be solved as a maximum cut problem on a planar graph which is a polynomial task.The focus of this paper is to use this approach for modern real-world chips. From the roughly two dozen wiring layers present, we take two adjacent ones for the via minimization. As a core-routine, we use a fast maximum cut algorithm on planar graphs. For being able to use the solutions in practice, we integrate practically relevant design rule constraints at the expense of potentially using further vias. Thus, our solution satisfies the additional constraints present in actual current designs. The computational results show that our implementation is fast on real-world instances as it usually computes a solution within a few minutes CPU time only. Moreover, often a considerable amount of vias can be saved

Distributed Algorithms in Wireless Sensor Networks

Wireless sensor networks (WSNs) are an emerging field of research which combines many challenges in distributed computing and network optimization. One important goal is to improve the functional lifetime of the sensor network using energy-efficient distributed algorithms, networking and routing techniques, and dynamic power management techniques. The energy consumption represents the major cost metric in almost all algorithms that are to be run in and on top of the WSN. Resulting from these constraints, various optimization criteria emerge. In our talk, we present some of the differences between energy-efficient wireless networking and network optimization usually considered by explaining key design features needed in the envisioned setting of wireless sensor networks

Local, Distributed Topology Control for Large-scale Wireless Ad-hoc Networks

In this document, topology control of a large-scale, wireless network by a distributed algorithm that uses only locally available information is presented. Topology control algorithms adjust the transmission power of wireless nodes to create a desired topology. The algorithm, named local power adjustment (LPA), does not rely on information about a node's position, and uses only two local broadcast messages per node to complete. The two objectives of the algorithm are minimizing the maximal and average power used by the nodes for the wireless transmissions. Additionally, the constraint of keeping the entire network connected by bidirectional communication links is imposed